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XMEGA A [MANUAL]
8077I–AVR–11/2012
bit will select only which calibration source to use for the DFLL. In addition, the actual clock source that is selected must
enabled and configured for the calibration to function.
7.11
Register Description – DFLL32M/DFLL2M
7.11.1 CTRL – DFLL Control register
Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 0 – ENABLE: DFLL Enable
Setting this bit enables the DFLL and auto-calibration of the internal oscillator. The reference clock must be enabled and
stable before the DFLL is enabled.
After disabling the DFLL, the reference clock can not be disabled before the ENABLE bit is read as zero.
7.11.2 CALA – DFLL Calibration Register A
The CALA and CALB registers hold the 13-bit DFLL calibration value that is used for automatic run-time calibration of the
internal oscillator. When the DFLL is disabled, the calibration registers can be written by software for manual run-time
calibration of the oscillator. The oscillators will also be calibrated according to the calibration value in these registers
when the DFLL is disabled.
Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this
register is written.
Bit 6:0 – CALA[6:0]: DFLL Calibration Bits
These bits hold the part of the oscillator calibration value that is used for automatic runtime calibration. A factory-
calibrated value is loaded from the signature row of the device and written to this register during reset, giving an oscillator
frequency approximate to the nominal frequency for the oscillator. The bits cannot be written when the DFLL is enabled.
7.11.3 CALB – DFLL Calibration register B
Bit
7
65
4
3
2
10
+0x00
–
ENABLE
Read/Write
R
RRRRR
R/W
Initial Value
0
Bit
765
43210
+0x02
–
CALA[6:0]
Read/Write
R/W
Initial Value
0
xxxxxxx
Bit
76543210
+0x03
–
CALB[5:0]
Read/Write
R/W
Initial Value
0
xxxxxx
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